RF amplifiers, including low-noise amplifiers (LNAs) and power amplifiers (PAs), are very crucial components in a wireless communication system. In a receiver, an RF signal received from an antenna passes a filter and then immediately encounters an LNA. Therefore, the linearity of the LNA significantly affects the dynamic range of the receiver. PAs are used to enhance the output powers of transmitters. A PA is supposed to have high operating efficiency and provide high-linearity output power to meet system requirements without dissipating significant power.
In order to reduce the power dissipation, an RF amplifier in a wireless communication system often uses a DC bias point (quiescent operating point) operated in the class AB mode. This is especially true for a power amplifier which is usually the most power-hungry element in a transmitter. The power added efficiency (PAE) of a PA directly affects how long a battery can last. A DC bias in the class AB operation can improve the PAE of a PA due to its low quiescent bias current. However, the load line of an amplifier operated in the class AB mode may run into a pinch-off region and result in a gain compression when the output power of the amplifier increases to a certain level. Said gain compression then leads to a saturation of the output power because the DC operating point of the class AB amplifier approaches the pinch-off region. As a result, the power gain of a class AB amplifier may be limited by the pinch-off region when the output power increases to a certain level.
To prevent the aforementioned gain compression phenomenon from happening, the quiescent bias current can be increased to ensure the amplifier operating in the desired mode. However, the increase of the quiescent bias current also leads to an extra DC power consumption at low power levels. The side effect of the extra DC power consumption is a PAE reduction.
FIG. 1 shows a conventional dynamic bias circuit for a PA disclosed in the U.S. Pat. No. 6,300,837. The bias circuit is suitable for a PA having a bipolar amplifying transistor, such as GaAs HBT or SiGe HBT or Si BJT. The amplifier can be operated in the class B or class AB mode. This bias circuit can enhance the maximum output power of an amplifier, and reduce DC power dissipation at low output power levels. It supplies a DC bias current to the base electrode of an amplifying transistor. In the bias circuit, there is a built-in power sensing circuit which acts as a current control current source or voltage control current source. As the input power increases, the power sensing circuit forces the bias circuit to produce more bias current. Therefore, the bias current supplied by the dynamic bias circuit increases with increasing input power level.
Referring to FIG. 1, the operation principle of a dynamic bias circuit is described in the following. Transistors 142 and 100 are the first and the second amplifying transistors. Both of them are operated in the class AB mode. Transistor 148, a power-sensing transistor, is also operated in the class AB mode. Collector current I1 of the power-sensing transistor 148, which flows into a current mirror 150, increases as the input power increases. The increase of collector current I1 results in an increase of output current I2 of current mirror 150, and hence the current flowing through a bias circuit 120 increases. This leads to an increase of base current I3 of transistor 123. I4 is the base current of the second amplifying transistor 100, which is about equal to (1+β)×I3, wherein β is the current gain of transistor 123. As can be seen from FIG. 1, I4 is the sum of the quiescent bias current used to control the second amplifying transistor 100 and the current contributed from power-sensing transistor 148. Therefore, the large-signal output power of the second amplifying transistor 100 is enhanced when the input power increases.
Though the aforementioned prior art improves maximum output power as well as power dissipation at low output power levels, it still consumes significant power due to the use of a bipolar amplifying transistors in the PA. The use of a bipolar amplifying transistor inevitably produces a non-zero quiescent bias current flowing through the bias circuit. As a result, it contributes to extra power dissipation. Moreover, it has a complex bias circuit and thus a high manufacturing cost There are more conventional dynamic bias boosting circuits for PAs disclosed in U.S. Pat. Nos. 6,414,553, 6,492,875, and 6,791,418. All these bias boosting circuits use one or more bipolar transistors, and have the same power dissipation problem resulted from the non-zero quiescent bias current.
The bias circuit for a conventional amplifier usually operates at a fixed DC bias voltage. In the case of an amplifier having a field effect transistor (FET) amplifying transistor, the bias circuit provides a fixed DC bias voltage to the gate electrode of the FET. This DC bias voltage does not change with the input or output power. The DC quiescent bias provided by the bias circuit determines whether the amplifier is operated in the class A or class AB mode. In U.S. Pat. No. 6,819,180, an adaptive bias control circuit is disclosed for an RF power amplifier having a lateral double-diffused metal-oxide semiconductor (LDMOS) FET as an amplifying transistor. Said adaptive bias control circuit comprises a second FET transistor whose gate and drain are connected together, and its source is coupled to a fixed voltage. This circuit connection causes the second FET transistor in the bias circuit to constantly draw current, and thus leads to extra power dissipation. Moreover, the DC bias voltage to the gate of the amplifying transistor decreases with increasing input power. This results in an undesirable power gain reduction.
Therefore, there exists a need for a power efficient and cost effective bias circuit to dynamically control the bias point of an RF amplifier for the purpose of improving the linearity of transfer characteristics and reducing power dissipation.